Branch prediction Microarchitecture

one barrier achieving higher performance through instruction-level parallelism stems pipeline stalls , flushes due branches. normally, whether conditional branch taken isn t known until late in pipeline conditional branches depend on results coming register. time processor s instruction decoder has figured out has encountered conditional branch instruction time deciding register value can read out, pipeline needs stalled several cycles, or if s not , branch taken, pipeline needs flushed. clock speeds increase depth of pipeline increases it, , modern processors may have 20 stages or more. on average, every fifth instruction executed branch, without intervention, s high amount of stalling.

techniques such branch prediction , speculative execution used lessen these branch penalties. branch prediction hardware makes educated guesses on whether particular branch taken. in reality 1 side or other of branch called more other. modern designs have rather complex statistical prediction systems, watch results of past branches predict future greater accuracy. guess allows hardware prefetch instructions without waiting register read. speculative execution further enhancement in code along predicted path not prefetched executed before known whether branch should taken or not. can yield better performance when guess good, risk of huge penalty when guess bad because instructions need undone.