Instruction pipelining Microarchitecture

one of first, , powerful, techniques improve performance use of instruction pipeline. processor designs carry out of steps above 1 instruction before moving onto next. large portions of circuitry left idle @ 1 step; instance, instruction decoding circuitry idle during execution , on.

pipelines improve performance allowing number of instructions work way through processor @ same time. in same basic example, processor start decode (step 1) new instruction while last 1 waiting results. allow 4 instructions in flight @ 1 time, making processor 4 times fast. although 1 instruction takes long complete (there still 4 steps) cpu whole retires instructions faster.

risc makes pipelines smaller , easier construct cleanly separating each stage of instruction process , making them take same amount of time — 1 cycle. processor whole operates in assembly line fashion, instructions coming in 1 side , results out other. due reduced complexity of classic risc pipeline, pipelined core , instruction cache placed on same size die otherwise fit core alone on cisc design. real reason risc faster. designs sparc , mips ran on 10 times fast intel , motorola cisc solutions @ same clock speed , price.

pipelines no means limited risc designs. 1986 top-of-the-line vax implementation (vax 8800) heavily pipelined design, predating first commercial mips , sparc designs. modern cpus (even embedded cpus) pipelined, , microcoded cpus no pipelining seen in area-constrained embedded processors. large cisc machines, vax 8800 modern pentium 4 , athlon, implemented both microcode , pipelines. improvements in pipelining , caching 2 major microarchitectural advances have enabled processor performance keep pace circuit technology on based.