Out-of-order execution Microarchitecture

the addition of caches reduces frequency or duration of stalls due waiting data fetched memory hierarchy, not rid of these stalls entirely. in designs cache miss force cache controller stall processor , wait. of course there may other instruction in program data available in cache @ point. out-of-order execution allows ready instruction processed while older instruction waits on cache, re-orders results make appear happened in programmed order. technique used avoid other operand dependency stalls, such instruction awaiting result long latency floating-point operation or other multi-cycle operations.